CD54HC297 loop equivalent, digital phase-locked loop.
Description
* Digital Design Avoids Analog Compensation Errors
* Easily Cascadable for Higher Order Loops
* Useful Frequency Range - K-Clock . . . . . . . ..
They contain all the necessary circuits, with the exception of the divide-by-N counter, to build first-order phase-lock.
* Digital Design Avoids Analog Compensation Errors
* Easily Cascadable for Higher Order Loops
* Useful Frequency Range - K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ) - I/D-Clock . . . . . . . . . . . . . ..
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